// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
/*
 * Copyright (C) 2023 rengaomin@allwinnertech.com
 */

#ifndef _DT_BINDINGS_RESET_SUN60IW2_H_
#define _DT_BINDINGS_RESET_SUN60IW2_H_

#define RST_BUS_ITS_PCIE0	0
#define RST_BUS_NSI		1
#define RST_BUS_NSI_CFG		2
#define RST_BUS_IOMMU0_SY	3
#define RST_BUS_MSI_LITE0_MBU	4
#define RST_BUS_MSI_LITE0_AHB	5
#define RST_BUS_MSI_LITE1_MBU	6
#define RST_BUS_MSI_LITE1_AHB	7
#define RST_BUS_MSI_LITE2_MBU	8
#define RST_BUS_MSI_LITE2_AHB	9
#define RST_BUS_IOMMU1_SY	10
#define RST_BUS_DMA0		11
#define RST_BUS_DMA1		12
#define RST_BUS_SPINLOCK	13
#define RST_BUS_MSGBOX0		14
#define RST_BUS_PWM0		15
#define RST_BUS_PWM1		16
#define RST_BUS_DBGSY		17
#define RST_BUS_SYSDAP		18
#define RST_BUS_TIMER0		19
#define RST_BUS_DE0		20
#define RST_BUS_DI		21
#define RST_BUS_G2D		22
#define RST_BUS_EINK		23
#define RST_BUS_DE_SY		24
#define RST_BUS_VE_DEC		25
#define RST_BUS_VE_ENC0		26
#define RST_BUS_CE_SY		27
#define RST_BUS_CE		28
#define RST_BUS_NPU_AHB		29
#define RST_BUS_NPU_AXI		30
#define RST_BUS_NPU_CORE	31
#define RST_BUS_GPU0		32
#define RST_BUS_DRAM0		33
#define RST_BUS_NAND0		34
#define RST_BUS_SMHC0		35
#define RST_BUS_SMHC1		36
#define RST_BUS_SMHC2		37
#define RST_BUS_SMHC3		38
#define RST_BUS_UFS_AXI		39
#define RST_BUS_UF		40
#define RST_BUS_UART0		41
#define RST_BUS_UART1		42
#define RST_BUS_UART2		43
#define RST_BUS_UART3		44
#define RST_BUS_UART4		45
#define RST_BUS_UART5		46
#define RST_BUS_UART6		47
#define RST_BUS_TWI0		48
#define RST_BUS_TWI1		49
#define RST_BUS_TWI2		50
#define RST_BUS_TWI3		51
#define RST_BUS_TWI4		52
#define RST_BUS_TWI5		53
#define RST_BUS_TWI6		54
#define RST_BUS_TWI7		55
#define RST_BUS_TWI8		56
#define RST_BUS_TWI9		57
#define RST_BUS_TWI10		58
#define RST_BUS_TWI11		59
#define RST_BUS_TWI12		60
#define RST_BUS_SPI0		61
#define RST_BUS_SPI1		62
#define RST_BUS_SPI2		63
#define RST_BUS_SPIF		64
#define RST_BUS_SPI3		65
#define RST_BUS_SPI4		66
#define RST_BUS_GPADC0		67
#define RST_BUS_THS0		68
#define RST_BUS_IRRX		69
#define RST_BUS_IRTX		70
#define RST_BUS_LRADC		71
#define RST_BUS_SGPIO		72
#define RST_BUS_LPC		73
#define RST_BUS_I2SPCM0		74
#define RST_BUS_I2SPCM1		75
#define RST_BUS_I2SPCM2		76
#define RST_BUS_I2SPCM3		77
#define RST_BUS_SPDIF		78
#define RST_BUS_DMIC		79
#define RST_USB_0_PHY_RSTN	80
#define RST_USB_0_DEVICE	81
#define RST_USB_0_EHCI		82
#define RST_USB_0_OHCI		83
#define RST_USB_1_PHY_RSTN	84
#define RST_USB_1_EHCI		85
#define RST_USB_1_OHCI		86
#define RST_USB_2		87
#define RST_BUS_PCIE0		88
#define RST_BUS_PCIE0_PWRUP	89
#define RST_BUS_SERDES_NOPPU	90
#define RST_BUS_SERDE		91
#define RST_BUS_GMAC0_AXI	92
#define RST_BUS_GMAC0		93
#define RST_BUS_GMAC1_AXI	94
#define RST_BUS_GMAC1		95
#define RST_BUS_VO0_TCONLCD0	96
#define RST_BUS_VO0_TCONLCD1	97
#define RST_BUS_VO0_TCONLCD2	98
#define RST_BUS_LVDS0		99
#define RST_BUS_LVDS1		100
#define RST_BUS_DSI0		101
#define RST_BUS_DSI1		102
#define RST_BUS_TCONTV0		103
#define RST_BUS_TCONTV1		104
#define RST_BUS_EDP		105
#define RST_BUS_HDMI_HDCP	106
#define RST_BUS_HDMI_SUB	107
#define RST_BUS_HDMI_MAIN	108
#define RST_BUS_DPSS_TOP0	109
#define RST_BUS_DPSS_TOP1	110
#define RST_BUS_VIDEO_OUT0	111
#define RST_BUS_VIDEO_OUT1	112
#define RST_BUS_LEDC		113
#define RST_BUS_DSC		114
#define RST_BUS_CSI		115
#define RST_BUS_VIDEO_IN	116
#define RST_BUS_APB2JTAG	117

#endif /* _DT_BINDINGS_RESET_SUN60IW2_H_ */
